? semiconductor components industries, llc, 2006 may, 2006 ? rev. 4 1 publication order number: nlsf302/d nlsf302 quad 2?input nor gate the nlsf302 is an advanced high speed cmos 2?input nor gate fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7.0 v, allowing the interface of 5.0 v systems to 3.0 v systems. features ? high speed: t pd = 3.6 ns (typ) at v cc = 5.0 v ? low power dissipation: i cc = 2.0 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2.0 v to 5.5 v operating range ? low noise: v olp = 0.8 v (max) ? function compatible with other standard logic families ? qfn?16 package ? latchup performance exceeds 300 ma ? esd performance: human body model; > 2000 v, machine model > 200 v ? chip complexity: 40 fets or 10 equivalent gates ? pb?free package is available* l l h h l h l h function table inputs output ab h l l l y *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com device package shipping ? ordering information nlsf302 = device code a = assembly location l = wafer lot y = year w = work week = pb?free package NLSF302MNR2 qfn?16 3000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. (note: microdot may be in either location) NLSF302MNR2g qfn?16 (pb?free) 3000/tape & ree l marking diagram qfn?16 mn suffix case 485g 16 nlsf 302 alyw 1 ??? ??? ???
nlsf302 http://onsemi.com 2 figure 1. logic diagram 1 5 y1 16 a1 1 b1 y4 y = a + b 3 y2 4 a2 5 b2 9 y3 7 a3 8 b3 13 10 a4 12 b4 13 14 15 16 5678 9 10 11 12 b3 b4 nc a4 y3 a3 gnd b2 y4 v cc y1 a1 b1 nc y2 a2 nlsf302 mn package (top view) 1 2 3 4 figure 2. pin assignment (qfn?16) ??????????????????????? ??????????????????????? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? dc supply voltage ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? 20 ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? 25 ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? 50 ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? ?????????????? ?????????????? ??? ??? ?????? ?????? ??? ??? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. recommended operating conditions parameter symbol min max unit ?????????????? ?????????????? dc supply voltage ??? ??? ???? ???? ??? ??? ??? ??? ?????????????? ?????????????? ??? ??? ???? ???? ??? ??? ??? ??? ?????????????? ?????????????? ??? ??? ???? ???? ??? ??? ??? ??? ?????????????? ?????????????? ??? ??? ???? ???? ??? ??? ??? ??? c ?????????????? ? ???????????? ? ?????????????? input rise and fall time v cc = 3.3 v 0.3 v v cc =5.0 v 0.5 v ??? ? ? ? ??? t r , t f ???? ? ?? ? ???? 0 0 ??? ? ? ? ??? 100 20 ??? ? ? ? ??? ns/v this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
nlsf302 http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? ???????? ? ?????? ? ???????? parameter ??????? ? ????? ? ??????? test conditions ??? ??? ???? ? ?? ? ???? v cc v ???????? ???????? c ??????? ??????? c ?? ?? ?? ??? ??? ???? ???? ??? ??? ??? ??? ???? ???? ???? ???? ???????? ???????? minimum high?level input voltage ??????? ??????? ??? ??? ???? ???? ???? ???? ??? ??? ??? ??? ???? ???? ???? ???? ?? ?? ???????? ? ?????? ? ???????? maximum low?level input voltage ??????? ? ????? ? ??????? ??? ? ? ? ??? v il ???? ? ?? ? ???? 2.0 3.0 to 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ??? ? ? ? ??? 0.50 v cc x 0.3 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.50 v cc x 0.3 ?? ?? ?? ???????? ? ?????? ? ? ?????? ? ? ?????? ? ???????? minimum high?level output voltage ??????? ? ????? ? ??????? v in = v ih or v il i oh = ?50 a ??? ? ? ? ? ? ? ? ? ? ??? v oh ???? ? ?? ? ???? 2.0 3.0 4.5 ???? ? ?? ? ???? 1.9 2.9 4.4 ??? ? ? ? ??? 2.0 3.0 4.5 ??? ? ? ? ??? ???? ? ?? ? ???? 1.9 2.9 4.4 ???? ? ?? ? ???? ?? ?? ?? ?? ?? v ??????? ? ????? ? ??????? v in = v ih or v il i oh = ?4 ma i oh = ?8 ma ???? ? ?? ? ???? 3.0 4.5 ???? ? ?? ? ???? 2.58 3.94 ??? ? ? ? ??? ??? ? ? ? ??? ???? ? ?? ? ???? 2.48 3.80 ???? ? ?? ? ???? ???????? ? ?????? ? ? ?????? ? ? ?????? ? ???????? maximum low?level output voltage ??????? ? ????? ? ??????? v in = v ih or v il i ol = 50 a ??? ? ? ? ? ? ? ? ? ? ??? v ol ???? ? ?? ? ???? 2.0 3.0 4.5 ???? ? ?? ? ???? ??? ? ? ? ??? 0.0 0.0 0.0 ??? ? ? ? ??? 0.1 0.1 0.1 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.1 0.1 0.1 ?? ?? ?? ?? ?? ??????? ? ????? ? ??????? v in = v ih or v il i ol = 4 ma i ol = 8 ma ???? ? ?? ? ???? 3.0 4.5 ???? ? ?? ? ???? ??? ? ? ? ??? ??? ? ? ? ??? 0.36 0.36 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.44 0.44 ???????? ? ?????? ? ???????? maximum input leakage current ??????? ? ????? ? ??????? v in = 5.5 v or gnd ??? ? ? ? ??? i in ???? ? ?? ? ???? 0 to 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ??? ? ? ? ??? 0.1 ???? ? ?? ? ???? ???? ? ?? ? ???? 1.0 ?? ?? ?? a ???????? ???????? ??????? ??????? ??? ??? ???? ???? ???? ???? ??? ??? ??? ??? ???? ???? ???? ???? ?? ?? a ????????????????????????????????? ????????????????????????????????? ac electrical characteristics (input t r = t f = 3.0ns) ????????? ? ??????? ? ????????? parameter ???????? ? ?????? ? ???????? test conditions ???? ???? ????????? ????????? c ?????? ?????? c ?? ?? ?? ???? ???? ??? ??? ???? ???? ???? ???? ??? ??? ???? ???? ????????? ? ??????? ? ? ??????? ? ????????? maximum propagation delay , input a or b to output y ???????? ???????? 0.3 v c l = 15 pf c l = 50 pf ???? ? ?? ? ? ?? ? ???? t plh , t phl ??? ??? ???? ???? ???? ???? ??? ??? ???? ???? ?? ?? ?? ?? ???????? ? ?????? ? ???????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ???? ? ?? ? ???? 3.6 5.1 ???? ? ?? ? ???? 5.5 7.5 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 6.5 8.5 ????????? ????????? ???????? ???????? ???? ???? ??? ??? ???? ???? ???? ???? ??? ??? ???? ???? ?? ?? ???? ? ?? ? ???? c pd typical @ 25 c, v cc = 5.0 v pf 15 1. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc / 4 (per gate). c pd is used to determine the no?load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0 ns, c l = 50 pf, v cc = 5.0v) characteristic symbol t a = 25 c uni t typ max quiet output maximum dynamic v ol v olp 0.3 0.8 v quiet output minimum dynamic v ol v olv ? 0.3 ? 0.8 v minimum high level dynamic input voltage v ihd 3.5 v maximum low level dynamic input voltage v ild 1.5 v figure 3. switching waveforms v cc gnd 50% 50% v cc a or b y t phl t plh *includes all probe and jig capacitance figure 4. test circuit c l * test point device under test output figure 5. input equivalent circuit input
nlsf302 http://onsemi.com 4 package dimensions 16 pin qfn case 485g?01 issue c 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ?? ?? ?? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 nlsf302/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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